Discontinuous pulse width drive modulation method and apparatus

ABSTRACT

Control systems, methods and power conversion systems are presented for reducing common mode voltages in AC motor loads driven by inverter PWM control using switching sequences with only active vectors where a first vector of each switching sequence differs by one phase switching state from a last vector of a switching sequence of an adjacent sector, along with enhanced deadtime compensation and reflected wave reduction techniques in providing pulse width modulated switching signals to a switching inverter.

BACKGROUND

The present invention relates generally to the field of power conversionsystems such as those used convert direct current (DC) power toalternating current (AC) power. More particularly, the present inventionrelates to systems and methods for using pulse width modulation (PWM)techniques capable of high speed switching of electrical energy to drivepower electronic devices, such as insulated gate bipolar transistors(IGBTs).

Electric drives are used in a wide range of applications. For example,drives incorporating power electronic switching circuits are used topower AC motors capable of converting electrical energy for use withcentrifuges, magnetic clutches, pumps and more generally, in electricmotor drive controllers that transform and condition incoming AC powerfor supply to motor drive circuitry. In certain motor drive circuits,PWM is utilized to redirect and rectify incoming AC power and to delivervariable DC or AC power, as well as in DC/AC and AC/AC conversion.Accordingly, PWM techniques may be used to switch the IGBTs on and offaccording to different phases of the incoming AC power. However, onedrawback of PWM drives is that they may experience high common-modevoltages.

BRIEF DESCRIPTION

A system and a method for using a discontinuous two-phase PWM method aredescribed herein that may enable a reduction in common-mode voltage(CMV) of a power conversion system, such as an electric motor drive. Thesystem and method described herein may utilize a single carrier wave(e.g., sinusoidal triangle wave) in combination with techniques such asspace vector modulation to selectively drive (e.g., turn on and off) theswitches of a motor drive, such as in an active front end (AFE) torealize improved reductions in CMV. Carrier wave PWM refers to the useof a carrier wave, such as the triangle wave, and a reference orfeedback signal. Comparator techniques may be used to compare thetriangle wave with the reference signal, resulting in a PWM signalsuitable for modulating or driving an electric motor. Space vectormodulation (SVM) and space vector with PWM (SVPWM) refers to the use ofdiagrams including eight possible output vectors or voltages. Sixvectors are active vectors while two vectors are zero vectors. Thevectors are divided using in a hexagonal model having six sectors, andthe model may then be used to define a switching sequence that uses onlythe active vectors suitable for reducing CMV.

Additionally, the techniques described herein may be used to compensatefor reflected waves, prevent polarity reversals, and compensate for deadtime. Reflected waves refer to the presence of certain waves travelingthrough, for example, system cabling. Increased cabling distances mayresult in wave pattern interference. Dead time refers to the effectassociated with a time between the actuation of one switch and theactuation of another switch, for example, from the same “leg” or pole ofthe power converter. Dead time may distort the voltage delivered to themotor. Polarity reversals refer to instantaneous reversal of thepolarity of the voltage delivered to the motor. Further, the techniquesdisclosed herein may be applied to an inverter and/or a rectifier of amotor drive, without the need to synchronize PWM carrier frequencies.Indeed, the techniques described herein are capable of converting inputpower to output power of a desired form, such as a multi-phase AC power,starting a motor, stopping a motor, regulating the speed of a motor,regulating motor torque, protecting against overloads or faults, and soforth.

In accordance with aspects of the present disclosure, a power conversionsystem is provided. The power conversion system includes a DC circuitconfigured to transmit DC power and an inverter coupled to the DCcircuit and configured to receive the DC power. The inverter alsoincludes one or more AC terminals for supplying AC power and an inverterswitching network comprising a plurality of inverter switches. The powerconversion system includes a switch controller that uses a first singlecarrier wave to control the inverter switching network for supplying theAC power.

In accordance with further aspects of the disclosure, a power conversionsystem that includes a DC bus configured to transmit a first DC power,and a rectifier comprising a rectifier switching network having aplurality of rectifier switches. The rectifier is configured to receiveAC input power and to deliver a second DC power to the DC bus. The powerconversion system also includes an inverter coupled to the DC bus andconfigured to receive the first DC power from the DC bus. The invertercomprises one or more AC terminals for supplying AC power and aninverter switching network having a plurality of inverter switches. Thepower conversion system also includes a switch controller. The switchcontroller uses a first single triangle carrier wave to control therectifier switching network for supplying the second DC power to the DCbus, and a second single triangle carrier wave to control the inverterswitching network for supplying the AC power.

In accordance with still other aspects of the disclosure, anon-transitory computer-readable medium is provided comprising codeadapted to calculate a pulse width modulation period T_(PWM), to receivea signal representative of one or more AC output phases of an inverter,to calculate a sector position of a reference vector in a space vectordiagram, the space vector diagram having six sectors, to derive a pulsewidth modulation (PWM) switching sequence based on the sector positionof the reference vector, to derive a max, a mid, or a min value based onthe received signal, to apply an active high modulation to the max andmin values, to apply an active low modulation to the mid value, and togenerate the PWM switching sequence by using a single carrier wave andthe applied active high modulation and active low modulation. Thegenerated PWM switching sequence comprises switching a switchingnetwork.

DRAWINGS

These and other features, aspects, and advantages of the presentinvention will become better understood when the following detaileddescription is read with reference to the accompanying drawings in whichlike characters represent like parts throughout the drawings, wherein:

FIG. 1 is a schematic diagram illustrating an exemplary power conversionsystem, according to certain aspects of the present disclosure;

FIG. 2 is a schematic diagram illustrating an exemplary IGBT switch foruse with the techniques set forth in the present disclosure;

FIG. 3 is an exemplary SVM diagram having six sectors and a rotatingreference vector, according to certain aspects of the presentdisclosure;

FIG. 4 is a block diagram illustrating an exemplary set of common-modereduction switching sequences for the six sectors in the diagram of FIG.3;

FIG. 5. is a timing diagram illustrating exemplary phase feedbacksignals or values and a triangle carrier wave, with selective use ofactive high or active low PWM, according to certain aspects of thepresent disclosure;

FIG. 6. is another timing diagram illustrating exemplary phase feedbacksignals or values and a triangle carrier wave, with selective use ofactive high or active low PWM, according to certain aspects of thepresent disclosure;

FIG. 7 is a timing diagram illustrating the mitigation of reflectedwaves and the prevention of polarity reversals, according to certainaspects of the present disclosure;

FIG. 8 is a timing diagram illustrating active high PWM deadtimecompensation, according to certain aspects of the present disclosure;

FIG. 9 is a timing diagram illustrating active low PWM deadtimecompensation, according to certain aspects of the present disclosure;and

FIG. 10 is a flow chart illustrating exemplary logic to obtaincommon-mode voltage reduction, according to certain aspects of thepresent disclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a three-phase power conversionsystem, such as a motor drive 10. The motor drive 10 may include arectifier circuit 12 coupled to an inverter circuit 14, which may beused to drive a three-phase motor 16. In the illustrated embodiment, therectifier circuit 12 and the inverter circuit 14 are controlled by aswitch controller 18, having a rectifier controller 20 and an invertercontroller 22. The rectifier controller 20 controls the rectifiercircuit 12 while the inverter controller controls the inverter circuit14. Three phases of AC power from the supply mains V_(A), V_(B), andV_(C) may be directed through the line reactors L_(A), L_(B), and L_(C),respectively. The line reactors L_(A), L_(B), and L_(C) are used asfilters to smooth converted power signals and to improve the harmonicsof the circuit. The AC power may then be converted into DC power by therectifier 12. In one embodiment, the rectifier 12 may provide for ACrectification and braking regeneration. The rectifier circuit 12 mayinclude a rectifier switching network having solid state switches S₁,S₂, S₃, S₄, S₅, and S₆. During rectification, the switches S₁-S₆ of thecircuit may be switched so as to convert the incoming AC power into DCpower. Common-mode voltage CMV generated by the rectifier circuit 12 maybe defined as the potential of the center node 26 (O) of the DC bus 24with respect to ground, and can be expressed asCMV_(R)=(V_(ro)+V_(so)+V_(to))/3. In one embodiment, the rectifiercontroller 22 may use a single carrier wave (e.g., triangle wave) todrive the switches S₁-S₆ by using a discontinuous PWM switching methodcapable of improved CMV reduction, dead time compensation, reflectedwave compensation, and the prevention of polarity reversal.

The DC power from the rectifier 12 is transferred to a common DC bus 24having a center node 26. The DC power may then be converted into ACpower by the inverter 14. A set of bus capacitors 28 and 30 may beconnected between the two DC bus lines and are used to create a lowimpedance source, which also helps filter DC ripples. The DC bus maythen transfer power to the inverter 14 for conversion to AC power. CMVmay be defined as a potential of the neutral point of the load (e.g.,motor 16) with respect to the center node 26 of the DC bus 24, and canbe expressed as CMV_(I)=(V_(uo)+V_(vo)+V_(wo))/3. The total CMVgenerated by the motor drive 10 may be defined as the potential of theneutral point of the load with respect to ground, and can be expressedasCMV=CMV_(I)−CMV_(R)=(V_(uo)+V_(vo)+V_(wo))/3−(V_(ro)+V_(so)+V_(to))/3.Fast switching time and high DC bus voltage levels may result in CMVwith high rise-time, which leads to high common-mode currents. Highcommon-mode currents may result in bearing problems and/or noisedeveloping in the driven motor. Accordingly, in certain embodiments, theinverter controller 22 may use a single carrier wave (e.g., trianglewave) to drive an inverter switching network having the switches S₇, S₈,S₉, S₁₀, S₁₁, and S₁₂. Indeed, the switching controller 18 may use adiscontinuous PWM switching method capable of improved CMV reduction,dead time compensation, reflected wave compensation, and prevention ofpolarity reversal.

The carrier frequency used to modulate the inverter 14 may beindependent of the carrier frequency used to modulate the rectifier 12.That is, PWM synchronization between the rectifier 12 and the inverter14 may not be required. Accordingly, a higher carrier frequency may beused in the rectifier 12 to optimize filter design, and a lower carrierfrequency may be used in the inverter 14 to increase rating at lowoutput frequencies. The inverter 14 may produce a multi-phase AC power,one phase of power for each pole u, v, and w. Accordingly, the motor 16may be operated by redirecting AC power through the poles u, v, and w.Control modalities of the switch controller 18 may thus start or stopthe motor, regulate the speed of the motor, regulate the motor's torque,and provide protection against overloads or faults.

FIG. 2 illustrates an IGBT-type switch 32. The switching devices S₁-S₆,and S₇-S₁₂ may be any suitable electrically-controllable switch, such asthe IGBT 32. The IGBT 32 may be controlled according to any suitabletype or form of switching signals from the switch controller 18. In theillustrated example, the IGBT 32 includes an anti-parallel or fly-backdiode 34 connected in parallel across the switching terminals 36 and 38.The IGBT 32 also includes a base or control gate terminal 40 that willbe connected to the switch controller 18 so as to receive acorresponding switching control signal to regulate the conductive stateof the switch. It is to be understood that otherelectrically-controllable switching devices may be used, such asthyristors (e.g., gate turn-off thyristor, integrated gate commutatedthyristor).

FIG. 3 is an exemplary SVM diagram 42. The SVM diagram 42 includes sixstationary active space vectors 100, 110, 010, 011, 001, and 101positioned counterclockwise around the periphery of the diagram 42 aswell as two stationary zero vectors 000 and 111 located at the diagramorigin. The active and zero vectors represent unique switching statesfor the switches S₁-S₆ of the rectifier 12 and/or the switches S₇-S₁₂ ofthe inverter 14. That is, when applied to the inverter 14, the firstdigit of the vector may correspond to the u phase, the second digit ofthe vector may correspond to the v phase, and the third digit of theinverter may correspond to the w phase. For example, the vector 110,when applied to the inverter 14, may denote that the upper switch of uphase is switched on, the upper switch of v phase is switched on, andthe lower switch of w phase is switched on. Likewise, the space vectordigits represent unique switching states for the rectifier 12. That is,when applied to the rectifier 12, the first digit of the vector maycorrespond to r phase, the second digit may correspond to s phase, andthe third digit may correspond to t phase.

The SVM diagram 42 also defines six triangular sectors (labeled sector 1through sector 6 in FIG. 3) positioned around the origin, each of whichis defined by a 60° angle having two edges sharing the common originendpoint and bifurcating the triangular segments corresponding to theactive space vectors 001-110. That is, each edge of a sector may be atthe approximate middle of a triangle defined by two adjacent activevectors in the depicted hexagon. For example, sector 1 is defined by afirst edge that bifurcates the triangle bounded by the active vectors100 and 110, and a second edge that bifurcates the triangle bounded bythe active vectors 100 and 101. To operate the rectifier 12 and/or theinverter 14, a controller, such as the switch controller 18 providesswitching control signals according to a selected switching sequence,such as the switching sequences depicted in FIG. 4 below. The selectedswitching sequence or pattern may correspond to the diagram sector inwhich a reference vector 44 is currently located. A desired motorposition and torque may be represented in terms of the magnitude andangle of the reference voltage vector 44. Accordingly, the selectedswitching sequence may drive the motor in accordance to the propertiesof the reference vector 44 (e.g., magnitude and angle).

In certain CMV reduction embodiments, each switching sequence, such asthe switching sequences depicted in FIG. 4, uses only active vectors.That is, the active space vectors 100, 110, 010, 011, 001, and 101 areused, and stationary space vectors 000 and 111 are not used.Additionally, the switching sequences may latch one of the phases (e.g.,u, v, or w for the inverter 14 and/or r, s, or t for the rectifier 12)as always on or always off. That is, one of the phase u, v, or w for theinverter 14 and/or r, s, or t for the rectifier 12 may always be eitherswitched on or off. This discontinuous two-phase PWM technique resultsin an improved reduction of CMV. As mentioned above in relation to FIG.1, CMV may be defined asCMV=(V_(uo)+V_(vo)+V_(wo))/3−(V_(ro)+V_(so)+V_(to))/3. Accordingly,CMV_(R) and CMV_(I) may theoretically include peak values approximatelyequal to ±V_(DC)/2, and CMV may include peak values approximately equalto ±V_(DC), where V_(DC) is the peak voltage of the DC bus. Theswitching techniques disclosed herein may reduce the peak CMV_(R) andthe peak CMV_(I) to approximately ±V_(DC)/6, and the peak CMV toapproximately ±V_(DC)/3. The minimum modulation index for the switchingtechnique disclosed herein is π/(3√{square root over (3)}) 0.61. Therectifier 12 is normally operated at a modulation index higher than theabove minimum value. To operate the inverter 14 at a modulation indexlower than the above minimum value, any of the well known prior artmodulation techniques can be used.

To implement this discontinuous two-phase PWM technique, the switchingpatterns may be arrived at in each of the six sectors 1-6 by a clockwiserotation of the vectors adjacent to or in the selected sector, followedby a counterclockwise rotation. Two such patterns may be arrived at foreach sector, one pattern is arrived at by beginning with acounterclockwise rotation of the active vector adjacent to the selectedsector, moving through the active vector in the center of the selectedsector, and ending in adjacent vector opposite to the starting vector.In this first pattern, the rotation is then reversed to a clockwiserotation moving back through the active vector in the center of theselected sector, and ending in the starting adjacent vector. Forexample, a first pattern (e.g., 101-100-110-100-101) for sector 1 may bearrived at by starting with adjacent vector 101, moving in acounterclockwise direction to vector 100, then ending in the adjacentvector 110, then returning in a clockwise direction to vector 100, andthen finishing with the starting adjacent vector 101. Likewise, a firstpattern (e.g., 100-110-010-110-100) for sector 2 may be arrived at bystarting with adjacent vector 100, moving in a counterclockwisedirection to vector 110, then ending in the adjacent vector 010, thenreturning in a clockwise direction to vector 110, and then finishingwith the starting adjacent vector 100.

A second pattern for each sector 1-6 that may be used with thediscontinuous two-phase PWM technique may be arrived at beginning with aclockwise rotation of the active vector adjacent to the selected sector,moving through the active vector in the center of the selected sector,and ending in adjacent vector opposite to the starting vector. In thissecond pattern, the rotation is then reversed to a counterclockwiserotation moving back through the active vector in the center of theselected sector, and ending in the starting adjacent vector. Forexample, the second pattern (e.g., 110-100-101-100-110) for sector 1 maybe arrived at by starting with adjacent vector 110, moving in clockwisedirection to vector 100, ending in vector 101, returning in acounterclockwise direction to vector 100, and stopping at vector 110.Likewise, the second pattern (e.g., 010-110-100-110-010) for sector 2may be arrived at by starting with adjacent vector 010, moving inclockwise direction to vector 110, ending in vector 100, returning in acounterclockwise direction to vector 110, and stopping at vector 010.

As can be observed in the two patterns of sector 1, the first digit ofthe two patterns has a value of one. Accordingly, the u phase is alwayson when using this sector for switching. Likewise, the two patterns ofsector 2 show that the third digit always has a value of zero.Accordingly, the phase w is always off when using this sector forswitching. Further, the sequential vectors selected by thisdiscontinuous two-phase PWM technique differ from one another by onlyone switching state. The same is true for the sequences corresponding tosectors 2-6. Thus, the exemplary switching sequences depicted in FIG. 4do not cause concurrent switching of two phase (or line states) statesin the rectifier 12 and/or the inverter 14, even at sector transitions(i.e., when moving from one sector to another sector), thereby furtherreducing common mode voltages at the motor 16.

FIG. 4 is a block diagram 46 illustrating an exemplary set of CMRswitching sequences for the six sectors in the SVM diagram 42 of FIG. 3.As shown in FIG. 4, the sectors 1-6 include switching sequences 48, 50,52, 54, 56, 58, 60, 62, 64, 66, 68, and 70. Switching sequences 48, 52,56, 60, 64, and 68 may have been arrived at beginning with acounterclockwise rotation, while switching sequences 50, 54, 58, 62, 66,and 70 may have been arrived at beginning with a clockwise rotation.Further, each of the switching sequences 48-70 uses only active vectors.For instance, the switching sequence 48 for sector 1 uses the activevectors 101, 100 and 110 that are adjacent to or in the sector 1. As aresult of using only the active vectors, the sequences reduce the CMVbecause the middle vectors 000 and 111 corresponding to peak voltagesare not used. Moreover, each of the two sequences for each sector 1-6,such as the sequences 48 and 50 begin and end with the same activevector (e.g., 101 or 110). This active vector differs by one phaseswitching state from the last vector of the switching sequencesassociated with its adjacent sectors (e.g., sectors 2 and 6). Forexample, the last vector 101 of sector 1 sequence 48 differs by oneswitching state from the first vector 100 in the sequence 52 of neighborsector 2. Likewise, the first vector 101 in sequence 48 for sector 1differs by only one switching state from the last vector 001 in thesequence 68 of the other adjacent sector 6.

Accordingly, more efficient and faster switching may be achieved byswitching from sequence to sequence. Indeed, when moving from a sequence(e.g., sequence 48 to another sequence (e.g., sequence 52), lessswitching energy may be used. In addition, the sequences 48-70 eachbegin in a counterclockwise direction, and finish in a clockwisedirection, or vice versa. Thus, the exemplary CMR switching sequences48-70 used by the switch controller 18 do not cause concurrent switchingof two phase states in the inverter 14 or line states in the rectifier12, even at sector transitions, thereby further reducing switchinglosses and polarity voltage reversals at the motor 120. In operation,the avoidance of the zero vectors may be effective in reducing commonmode voltages at the motor 16 load. Accordingly, the switching sequences48-70 are referred to as CMR sequences, and PWM using these is referredto as discontinuous CMRPWM. It is to be noted that any one of theswitching patterns of FIG. 4 may be generated using the method describedabove with respect to FIG. 3. Further, a controller, such as thecontrollers 18, 20, and 22, may be capable of using switching schemescorresponding to the SVM diagram 42 and the sector switching methodologyto modulate the rectifier 12 and/or the inverter 14. Further, the methoddescribed in relation to FIG. 3 may include non-transitory machinereadable code or computer instructions that may be used by a computingdevice (e.g., controllers 18, 20, and 22) to transform computed orsensor inputs, such as phase value inputs, into outputs, such asswitching outputs suitable for driving switches (e.g., S₁-S₁₂).

FIG. 5 illustrates an embodiment of a timing diagram 72 that may be usedto generate the sequences 48-70 of FIG. 4, showing exemplary phasefeedback signals or values labeled max 74, mid 76, and min 78, alongwith a single triangle carrier wave 80 (e.g., sine triangle wave).Indeed, a single carrier wave 80 may be used in conjunction with aderivation of max 74, mid 76 and min 78 to derive any one of theswitching patterns shown in FIG. 4. In the depicted diagram 72, the max74, mid 76, and min 78 curves represent the three output phase values Φ(e.g., u, v, and w for the inverter 14 or r, s, and t for the rectifier12) at a given point in time when the feedback signals or values areobtained by the switch controller 18. The three modulating gate signalsare used as shown in the timing diagram 72, in which G represents thephase switching function used to generate a switching sequence, forexample, sequence 48 of sector 1 (e.g., 101, 100, 110, 100, and 101). Itis to be noted that while conventional PWM techniques exclusively employactive high PWM (e.g., gating signal high state when the modulatingsignal is greater than the triangle wave such that the upper phaseswitch is on and the lower phase switch is off), the illustrated CMRPWMtechnique employed in the controller 18 selectively employs both activehigh (AH) and active low (AL) modulation. In AL modulation, the upperphase switch (e.g., switch S₇, S₈, S₉, or switch S₁, S₂, S₃) is turnedoff and the lower phase switch (e.g., switch S₁₀, S₁₁, S_(12,) or switchS₄, S₅, S₆) is turned on when the modulating feedback signal or valuewave is greater than the triangle carrier wave 80.

In one embodiment, the max 74, mid 76 and min 78 sets of signals areused based on the received output phase values Φ (e.g., u, v, and w forthe inverter 14 or r, s, and t for the rectifier 12), as depicted. AHmodulation is used with the max 74 and the min 78 modulating feedbacksignals or value waves (e.g., u and v signals in the depicted diagram72), and AL modulation is used in the mid 76 feedback signal or valuewave (e.g., w signal in the depicted diagram). Consequently, thegenerated function G_(u) will result in upper phase switch S₇ beingturned on and the lower phase switch S₁₀ being turned off when the usignal is greater than the triangle wave 80. In the depicted timinginterval, the u signal is always greater then the triangle wave 80.Accordingly, G_(u) is set to unity such that the upper phase switch S₇is turned on and the lower phase switch S₁₀ is turned off during thedepicted time interval of the diagram 72.

The min modulating signal or value wave 78 (e.g., v) is also used inconjunction with AH modulation. Accordingly, when the min level 78 isgreater than the triangle wave 80 (e.g., between time 82 and time 84),the value for G_(v) will be a unity. Likewise, the value for G_(v) willbe a zero outside of the time interval between time 82 and time 84, asillustrated. The mid modulating signal or value wave (e.g., 1−w) is usedin conjunction with AL modulation. Accordingly, when the mid level isgreater than the triangle wave 80 (e.g., between time 86 and time 88),the value for G_(w) will be a zero. When the mid level is not greaterthan the triangle wave (e.g., before time 86 and after time 88), thevalue for G_(w) will be unity. Indeed, the use of the techniquedescribed herein allows for a generation of all of the switchingpatterns shown in FIG. 4.

FIG. 6 is a timing diagram 90 that further illustrates the use of asingle triangle carrier wave 92, and assignments to max 94, mid 96, andmin 98, to generate a switching pattern. More specifically, FIG. 6illustrates the generation of the switching pattern 54 of sector 2. Asmentioned above, AH modulation is used for the max 94 and the min 98waves. Accordingly, G_(u) will have values set to unity when the max 94values are greater than the triangle wave 92 (e.g., between time 100 andtime 102). The G_(u) values before time 100 and after time 102 will thenbe set to zero. The min 98 values are latched at zero, and thus min 98will never be greater than the triangle wave 92. Consequently, G_(w)will be set to zero during the illustrated time. The mid 96 signal orvalue wave (e.g., 1−v) will undergo AL modulation. During AL modulation,the mid 96 level will be compared to the triangle wave 92, and if themid 96 level is greater than the triangle wave 92 (e.g., between time104 and time 106), the value for G_(v) will be set to zero. Asillustrated, the use of a single triangle carrier wave 92, andassignments of the observed output phase values Φ, may result in thegeneration of the switching pattern 54 (e.g., counterclockwise pattern)of sector 2. It is to be noted that any one of the switching patterns ofFIG. 4 may be generated using the method described above with respect toFIGS. 5 and 6. Further, a controller, such as the controllers 18, 20,and 22, may be capable of using the single triangle carrier wave 92 andthe observed phase values Φ to switch the rectifier 12 and/or theinverter 14. Further, the method described in relation to FIGS. 5 and 6may include non-transitory machine readable code or computerinstructions that may be used by a computing device (e.g., controllers18, 20 and 22) to transform sensor inputs, such as phase value inputs,into outputs, such as switching outputs suitable for driving switches(e.g., S₁-S₁₂).

FIG. 7 depicts an embodiment of the timing diagram 72 with the additionof a line-to-line output voltage curve V_(vw). That is, the voltagecurve V_(vw) may result from the modulation of the rectifier 14 by usingthe illustrated switching pattern 48 of sector 1. As the modulatingwaveform v approaches w, for instance, then V_(vw) approaches zero,where the resulting pulse width modulation can lead to an undesirablepolarity reversal (i.e., direct transition from positive to negative orvice versa). In normal operation, absent reflected wave compensation,all of the phase voltages will cross one another periodically, and willbe close to one another just before and just after they cross. Absentreflected wave compensation, moreover, whenever this occurs, a directtransition in the line-to-line voltage output from positive to negativewill happen, resulting in creation of a reflected wave in the cablebetween the power conversion system 10 and the motor 16, with the motor16 experiencing potentially high voltages. However, polarity reversalmay be eliminated and reflected waves may also be reduced or eliminatedby using the method as described below.

A limit on the timing in the resulting line-to-line voltage curve V_(vw)(and curves V_(uv) and V_(wu)) may be imposed in order to eliminatepolarity reversal and to reduce or eliminate reflected waves. That is,the duty cycle may be adjusted so that certain conditions are met. Whenin sectors 1, 3, and 5 of the SVM diagram, a value of min−mid should begreater than (2*T_(dwell/)T_(PWM)), where T_(dwell) is a predetermineddwell time and T_(PWM) is the PWM period. Also, when in sectors 1, 3,and 5 of the SVM diagram, min should be greater than T_(dwell/)T_(PWM).When in sectors 2, 4, and 6 of the SVM diagram, max−mid should begreater than (2*T_(dwell/)T_(PWM)). Likewise, when in sectors 2, 4, and6 of the SVM diagram, max should be less than (1−T_(dwell/)T_(PWM)). Inthis implementation, the timing in the voltage curves V_(vw), V_(uv),and V_(wu) are held at all times through selective adjustment of one ormore of the phase signals or values Φ. This prevents direct transitionfrom positive to negative in the switching patterns for each phase, andadvantageously mitigates reflected waves in conjunction with theswitching sequences of FIG. 4. Accordingly, unwanted high voltageswitching pulses may be reduced or eliminated.

The reflected wave reduction and polarity reversal prevention methoddescribed above may accumulate reflected wave adjustment amounts foreach phase signal or value Φ. Accordingly, the method may adjust one ormore feedback signals or values Φ higher or lower in a subsequent PWMperiod Tp_(PWM) to compensate for the reflected wave reductionadjustments in a previous PWM period. In other words, any accumulatedvolt-second differences due to imposing the conditions described abovewith respect to FIG. 7 may be compensated in the next PWM period. Toavoid distortion, the compensating adjustment accounts for anaccumulated volt-second error (e.g., a difference in switch on-time),and compensates by that amount in the next PWM period by again adjustingthe modulating signals the other way.

FIG. 8 illustrates a timing diagram 110 that may be used to selectivelyraise a feedback signal or value Φ′ above the uncompensated signal orvalue Φ for AH PWM control, thus providing for deadtime compensation. Asa result, a curve 112 representing the adjusted signal/value Φ′ crossesa carrier triangle at a higher value than does an uncompensated curve116, and thus the active high modulation causes the creation of aswitching pulse in curve 118 of FIG. 8 with the dead time andcompensation time delayed relative to an ideal case curve 120, buthaving the same pulse width Φ·Ts. This represents an improvement overthe uncompensated case shown in curve 122 in FIG. 8, which has adifferent (shorter) pulse width, thereby causing output voltagedistortion. In the illustrated embodiment, deadtime compensation mayoccur by selectively adjusting the feedback signals or values Φaccording to the following equation (1) for active high pulse widthmodulation:

φ′=φ+sign(i _(φ))*(T _(d) /T _(PWM))   (1)

where i_(Φ) is a corresponding phase current, T_(d) is a predetermineddeadtime value (e.g., 2 μsec in one example), and T_(PWM) is a pulsewidth modulation period (e.g., 500 μsec). For active low modulation, thecompensation is described in more detail below with respect to FIG. 9.

FIG. 9 illustrates a timing diagram 126 that may be used to compensatefor deadtime during AL PWM modulation. The diagram 126 of FIG. 9 showsthe carrier waveform 128, the uncompensated phase signal or value 130(Φ) and the compensated phase signal or value 132 (Φ′). As seen in thisactive low modulation case, without compensation, the deadtime includedin the resulting pulse curve 134 results in a pulse width which islonger than that of the ideal curve 136. In the illustrated embodiment,deadtime compensation may occur by selectively adjusting the feedbacksignals or values Φ according to the following equation (2) for activelow pulse width modulation:

φ′=φ−sign(i _(φ))*(T _(d) /T _(PWM)).   (2)

However, through change in the polarity of this compensation equation(2) for the active low modulation case, the curve 138 showing theresulting switching pulse for the case with the deadtime and thecompensation, the pulse width is maintained the same as the ideal case,while the entire pulse is shifted in time. In this manner, the adjustedfeedback signals or values Φ′ are generated by the deadtime compensationmethod described herein prior to using the PWM switching techniquesdescribed above. By this technique, the optional sector boundarydeadtime compensation is selectively performed if a sector transition isoccurring. A logic described in more detail below with respect to FIG.10 further describes the use of the techniques presented herein.

FIG. 10 is an embodiment of a logic 140 that may use the techniquesdescribed herein, including the use of the SVM diagram, the trianglewave switching techniques, polarity reversal prevention and reflectivewave reduction techniques, and deadtime compensation techniquesdescribed with respect to FIGS. 1-9 above. The logic 140 may includenon-transitory machine readable code or computer instructions that maybe used by a computing device (e.g., controllers 18, 20 and 2) totransform sensor inputs, such as phase value inputs, into outputs, suchas switching outputs suitable for driving switches (e.g., S₁-S₁₂). A newPWM period T_(PWM) may begin at block 142 The T_(PWM) period may be anysuitable period, such as a period of 500 μsec with a resultant 2 kHzfrequency (i.e., T_(PWM)=1/frequency). Signals for the AC phase outputsΦ (e.g., u, v, and w) may be derived (block 144), by one of severalcontrol methods well known in the art. In certain embodiments, thederivation of signals based on the AC phase outputs Φ of the inverter 14may include determining the location of the reference vector 44 in theSVM diagram 42. For instance, the desired motor position and torque maybe represented in terms of the magnitude and angle of the referencevector 44 for inverter 14. A controller, such as the controller 22, maygenerate signals or values which represent the AC phase outputs Φ (e.g.,u, v, and w) of the inverter 14 based on the reference vector 44. Incertain embodiments, the derivation of signals may be based on the ACphase outputs Φ (e.g., r, s, and t) of the rectifier 12, and may alsoinclude determining the location of the reference vector 44 in the SVMdiagram 42. For instance, the desired voltage of the common DC bus 24may be represented in terms of the reference vector 44 for rectifier 12.Similarly, a controller, such as the controller 20, may generate signalsor values which represent the AC phase outputs Φ (e.g., r, s, and t) ofthe rectifier 12 based on the reference vector 44. Accordingly, themethod described herein is capable of controlling the rectifier 12and/or the inverter 14 by using a reference vector 44 and a SVM diagram42.

If the derived signals indicate that the reference vector 44 is at asector boundary transition, then the logic 140 may accumulate anadjustment value for use in the next T_(PWM) period (block 146) asdescribed in more detail above with respect to FIG. 7. Common-modereduction PWM may be applied (block 148) by deriving a desired PWMswitching pattern based on the derived AC phase outputs Φ, the SVMdiagram 42, and the sector of the SVM diagram 42 having the referencevector 44. Such a switching pattern may enable a reduction incommon-mode voltage.

In certain embodiments, a deadtime compensation adjustment (block 150)may be used as described above with respect to FIGS. 8-9. The deadtimecompensation adjustment may reduce or eliminate, for example, outputvoltage distortions, resulting in a smoother and more efficient motordrive. An adjustment to prevent polarity reversals and to reduce oreliminate reflected waves may be used (block 152), as described in moredetail with respect to FIG. 7. Any accumulated adjustments, for example,adjustments due to sector boundary transitions, may be compensated for(block 154). The logic 140 may then generate PWM switching signals, forexample, by assigning the u, v, and w phases to a max, mid, and min setof values, as described above with respect to FIGS. 5 and 6. An AHmodulation may then be applied to the max and min values, and an ALmodulation may be applied to the mid value. The max, mid, and min valuesmay then be compared to the triangular carrier wave, for example, byusing a single compare register per phase u, v, w. The comparison maythen generate a PWM switching pattern suitable for controlling therectifier and/or inverter switches. Further, the switching pattern mayenable a reduction of common-mode voltage by avoiding the use of vectors000 and 111. The logic 140 may then iterate or loop to begin a new PWMperiod T_(PWM) (block 142).

While only certain features of the invention have been illustrated anddescribed herein, many modifications and changes will occur to thoseskilled in the art. It is, therefore, to be understood that the appendedclaims are intended to cover all such modifications and changes as fallwithin the true spirit of the invention.

1. A power conversion system comprising: a DC circuit configured totransmit DC power; an inverter coupled to the DC circuit and configuredto receive the DC power, the inverter comprising one or more ACterminals for supplying AC power and an inverter switching networkcomprising a plurality of inverter switches for converting the DC powerto the AC power; and a switch controller, wherein the switch controlleruses a first single carrier wave to control the inverter switchingnetwork for supplying the AC power, and wherein the switch controllerapplies control signals to the inverter switching network in accordancewith a selected switching sequence corresponding to a desired sector ofa switching scheme in which a reference vector is currently located, theswitching scheme corresponding to the reference vector in a space vectormodulation scheme having six stationary active space vectors around theperiphery and two stationary zero vectors at an origin, the schemehaving six triangular sectors positioned around the origin, each sectordefined by a 60° angle having two edges sharing a common origin endpointand bifurcating triangular segments corresponding to the six activespace vectors.
 2. The system of claim 1, wherein the switch controlleruses an active high modulation and an active low modulation to controlthe inverter switching network for supplying the AC power.
 3. The systemof claim 2, wherein the active high modulation is applied to a max and amin wave, and the active low modulation is applied to a mid wave.
 4. Thesystem of claim 3, wherein the one or more AC terminals comprise a u, v,and w terminals, and wherein the max, mid and min waves are derived fromthe u, v, and w terminals.
 5. The system of claim 1, comprising arectifier coupled to one or more AC mains and to the DC circuit, therectifier configured to provide the DC power to the DC circuit.
 6. Thesystem of claim 5, wherein the rectifier comprises a rectifier switchingnetwork comprising a plurality of rectifier switches.
 7. The system ofclaim 6, wherein the switch controller uses a second single carrier waveto control the rectifier switching network for supplying the DC power.8. The system of claim 5, wherein controller uses a first frequency tocontrol the inverter switching network and a second frequency to controlthe rectifier switching network.
 9. The system of claim 8, wherein thefirst and the second frequencies are not equal to each other.
 10. Thesystem of claim 6, wherein the switch controller applies control signalsto the rectifier switching network in accordance with the selectedswitching sequence corresponding to the desired sector of a switchingscheme in which the reference vector is currently located.
 11. Thesystem of claim 10, wherein the switch controller comprises a reflectedwave reduction component operative at each pulse width modulation periodTPWM to determine a max, a mid, and a min value based on the one or moreAC terminals and to adjust a duty cycle for sectors one, three, and fivebased on the relationships:(min−mid)>2*(Tdwell/TPWM); andmin>Tdwell/TPWM; and to adjust a duty cycle for sectors two, four, andsix based on the relationships:(max−mid)>2*(Tdwell/TPWM); andmax<1−Tdwell/TPWM; where Tdwell is a predetermined dwell time.
 12. Apower conversion system comprising: a rectifier comprising a rectifierswitching network having a plurality of rectifier switches configured toreceive AC input power and to convert the AC input power to DC powerapplied to a DC bus; an inverter configured to receive the DC power fromthe DC bus, the inverter comprising an inverter switching network havinga plurality of inverter switches configured to receive the DC power andto convert the DC power to output AC power; and a switch controllerconfigured to control the rectifier switching network for conversion ofthe AC input power to the DC power based upon a first single trianglecarrier wave, and to control the inverter switching network forconversion of the DC power to the output AC power based upon a secondsingle triangle carrier wave, wherein the switch controller appliescontrol signals to the inverter switching network or to the rectifierswitching network in accordance with a selected switching sequencecorresponding to a desired sector of a switching scheme in which a firstreference vector is currently located, the switching schemecorresponding to the first reference vector in a space vector modulationscheme having six stationary active space vectors around the peripheryand two stationary zero vectors at an origin, the scheme having sixtriangular sectors positioned around the origin, each sector defined bya 60° angle having two edges sharing a common origin endpoint andbifurcating triangular segments corresponding to the six active spacevectors.
 13. The system of claim 12, wherein the first single trianglecarrier wave and the second single triangle carrier wave have differentcarrier wave frequencies.
 14. The system of claim 12, wherein the switchcontroller uses an active high modulation and an active low modulationto control the rectifier switching network, the inverter switchingnetwork, or both.
 15. The system of claim 12, wherein the switchcontroller applies control signals to the rectifier switching network inaccordance with the selected switching sequence corresponding to thedesired sector of a switching scheme in which a second reference vectoris currently located.
 16. The system of claim 15, wherein the switchcontroller comprises a reflected wave reduction component operative ateach pulse width modulation period TPWM to determine a max, a mid, and amin value based on the one or more AC terminals and to adjust a dutycycle for sectors one, three, and five based on the relationships:(min−mid)>2*(Tdwell/TPWM); andmin>Tdwell/TPWM; and to adjust a duty cycle for sectors two, four, andsix based on the relationships:(max−mid)>2*(Tdwell/TPWM); andmax<1−Tdwell/TPWM; where Tdwell is a predetermined dwell time.
 17. Anon-transitory computer-readable medium comprising code adapted to:calculate a PWM period TPWM; receive a signal representative of one ormore AC output phases of an inverter, of a rectifier, or a combinationthereof; calculate a sector position of a reference vector in accordancewith a space vector switching scheme having six sectors; derive a PWMswitching sequence based on the position of the reference vector; derivea max, a mid, or a min value based on the received signal; apply anactive high modulation to the max and min values; apply an active lowmodulation to the mid value; generate the PWM switching sequence byusing a single carrier wave and the applied active high modulation andactive low modulation; and apply the PWM switching sequence to aswitching network.
 18. The non-transitory computer-readable medium ofclaim 17, wherein the switching network comprises an inverter switchingnetwork.
 19. The non-transitory computer-readable medium of claim 17,wherein switching network comprises a rectifier switching network. 20.The non-transitory computer-readable medium of claim 17, wherein thespace vector switching scheme comprises six stationary active spacevectors around the periphery and two stationary zero vectors at anorigin, the six sectors positioned around the origin, each sectordefined by a 60° angle having two edges sharing a common origin endpointand bifurcating triangular segments corresponding to the six activespace vectors.